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Look Ma, NO POTS!

Started by Loudthud, September 25, 2012, 10:10:37 PM

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KMG

QuoteThe servo integrator time constant in fact is too fast !!!
It's right!
Some results of simulating two JFET stages with & without servo matched by gain & operating point. Both works without "grid current"
V(out2), V(bias2), V(servo2) - vith servo loop.
V(out1), V(bias1) - vithout servo loop.
First - oscillating of servo loop due to improper loop parameters.
Second - as I said, servo loop increases operating point shift even in steady loop state (noservo_servo_end.jpg).

Loudthud

I did some experiments with a matched pair of J201s. (Guessing Idss within 2%, Vgoff within 5%). I used a 1.5K Source resistor on one side and the servo circuit on the other. 33uF capacitors bypassed the Sources. To be fair, I used a dual 50K pot to adjust the Drain resistor of both JFETs. That way when the pot was adjusted to give equal Drain voltage at DC, both JFETs would have very close to the same gain. The generator was connected directly to the Gates, no stopper and no coupling cap (important). Signals with Hi/Lo times of 40/60, 60/40, 20/80 and 80/20 at amplitudes of 200mV and 600mV were applied at 1KHz. At 100Hz you could start to see a little tilting on the servo side Drain, maybe the time constant needs to be longer,

Source voltage was measured for each duty cycle at supply voltages of 9V, 20V and 30V. In the vast majority of cases the shift in Source voltage taken as a percentage of change from the DC value was something less than twice as much in the servo circuit. I plan to retest with a coupling cap between the generator and the Gates. This should make the integrator see a consistant DC Source voltage and only shift bias when the signal clips.

In the interest of full disclosure, changes had to be made in the circuit at 30V. 33K was added in series with both sides of the Drain pot and 680 ohms added from Source to ground on the servo side because the opamp couldn't swing low enough with the 1K between it's output and the Source.

Opamp selection: A TL072 could be used but they don't like the output to swing very close to the rail. That could be fixed with a resistor from the Source to ground. A JFET input opamp would allow the integrator resistor to be increased. I'm sure better parts are available.

KMG

Schematic of simulation project & waveforms.

Roly

Quote from: J M Fahey
talking about different subjects !!
...
in fact that Op Amp + FET stage *can* oscillate (and probably will if given proper loop gain and phase shift).
...
The servo integrator time constant in fact is too fast !!!

Yep.

Just assembled in LTSpice; will poke with stick to see what it takes to get it to bite.  Given that there is only a small trace of 440Hz at the op-amp output, if this is going to oscillate I expect it to be at a very low frequency, slow "motorboating".

Well we all seem to be in agreement on this point.  I would rather see a few seconds time constant.


My model used a 2N3819 (since I don't have the MPF102 model on this 'puter, but I think this is close) and the LM324 because a) its output goes to ground and b) is slow.
If you say theory and practice don't agree you haven't applied enough theory.

J M Fahey

@ Roly: maybe it's not enough for steady state oscillation, but hit it with a single narrow pulse (say, 1V peak) and watch it ring.
Not at an audio freq. but way below.
I do not simulate (too modern for my abilities) but test designs (actual components on a wood, nails and bare wire breadboard) by wreaking havoc  touching some input with my finger and listening to and scoping what happens.
Old school? You bet !!  ;)

@ loudthud.
Yes, maybe you can not pull that source resistor down enough even by straight grounding it, and it would not be an Op Amp defect, of course.
At least for the experiment, hook the Op Amp to +/-15V rails, so it can sink below ground if needed, and see what happens.

Loudthud

Quote from: J M Fahey on October 02, 2012, 03:48:50 AM
@ loudthud.
Yes, maybe you can not pull that source resistor down enough even by straight grounding it, and it would not be an Op Amp defect, of course.
At least for the experiment, hook the Op Amp to +/-15V rails, so it can sink below ground if needed, and see what happens.

The circuit I copied from used +/- 15V supplies, but I'm committed to a single rail power at the moment. It's easy to tell if the opamp is out of gas, the opamp inputs will be at different DC voltages because the loop isn't closed. The resistor to ground across the source cap works fine. The JFETs I'm working with need at least 3V bias, not a problem for the opamp. At times I see low frequency ringing on the opamp output, but if the R1/R2 voltage divider is set properly, the shift in bias point is minimal. Maybe a small resisitor in series with the source cap would improve phase margin. I'm allowing the preamp rail to sag and that also effects the bias point.

Roly

@JM - Yes, well I have been known to say the ultimate simulation is when you build it.   ;)

I've just had a rather instructive episode.  I was asked to knock up a FET buffer with isolated transformer output.

The actuality came very close to the sim with only a couple of minor variations, one of which was a small but unpredicted rise in response up into the supersonic, but hardly worth talking about.

What really surprised me was that I tried a small cheap 3k:3kCT tranny purely on spec, with no strong hope that it would be sufficient.  I think these were originally used as driver transformers in small push-pull transistor amps, and I've often wondered why these driver and output transformers are still available cheaply when amps like that haven't been made for years, at least since the LM380 appeared.

Well I've got 2.3Megs presented to the guitar, no surprise there, but out of the tranny I'm getting 40Hz to 88kHz (my upper measurement limit) +/-1dB on a volt in.  NAD is -80dB at 100, 1k and 10k, and magnetic sensitivity to external fields is very low - all way better than I expected.

I've long been a "birdsnest" guy, throw it up against the universe and see what sticks, but sims have became part of my process 'coz I can't physically mock up every circuit that gets thrown at me on a forum.

{Following the floods here we had an object example of what happens if you feed a sim garbage data - you get garbage results!  These guys never heard of "GIGO".}


@Loudthud - sometimes it pays to relax one of your constraints for a while until you get a better handle on the problem, i.e. introduce a -ve op-amp supply for the time being so you can see the full sweep of your results and not have the bottom half hidden by being clipped off.  When you can see the whole picture an answer as to how to do it with a single supply may present itself (or it may emerge that the complication of providing a -ve supply may be worth it).
If you say theory and practice don't agree you haven't applied enough theory.

Loudthud

I'm not seeing any problems with a single rail design. The opamp is happy. Time constants could use a little tweeking, but a negative rail won't fix that. JFETs really start to open up when you get above 15V. All I can say is that a single rail design is more tube like, warts and all :) The subsonic artifacts of a tube amp are often overlooked.

Now I need a chip power amp with 100K input impedance (at least) and a Presence control.


Roly

Okay, a couple of sims in passing.  These are plots of what happens when the FET-servo is presented with a step to try and get some insight into what the low frequency stability is like.

The first is a 1 volt step up followed by the same down again after half a second.  Note that I have extended the time constant of the op-amp integrator from 0.1uF to 1uF.

The second is perhaps more a realistic 100mV step.

In the first case we can see that the FET saturates/limits for a significant time (due to having a gain of x30, similar to a 12AX7, but with a limited voltage swing available in the Drain circuit).

In the second case the Drain circuit doesn't actually saturate/limit but there is still that well damped oscillation.

I don't know that this proves anything, other than confirming what we would expect anyway, but it does suggest to me that input DC coupling might not be a good idea, and that a suitable coupling cap should be used with a much shorter time constant than the integrator servo loop.
If you say theory and practice don't agree you haven't applied enough theory.

J M Fahey

@ Roly. That's the point.
Time constants should be chosen to work for you, not against.

@ loudthud
QuoteJFETs really start to open up when you get above 15V. ..... The subsonic artifacts of a tube amp are often overlooked. ....  Now I need a chip power amp with 100K input impedance (at least) and a Presence control.
Agree, I use FETS with as much as they can stand.
At least 25V and a few types as high as 40V.
Nothing new, it's what those killer old Yamaha and Roland "Twin type" amps did. And old Randalls too.
Subsonic artifacts: although themselves can't be heard, mixed with audio they produce a very audible "tremolo type" modulation.
How?
Suppose a FET (or transistor, or Op Amp) has, say, 25Vpp swing capacity, and is clipping, so it's clamped at that value ... and you add a, say, 8Hz subsonic.
Yea, not a steady oscillation but a ringing waveform.
Say it goes from 20Vpp down.
The audible signal will have only 5Vpp available, and will be modulated, like it or not, by the 20Vpp subsonic, same as having an 8 Hz tremolo, simple as that.
That said "tremolo" lasts a few milliseconds is true, but we can't deny it adds "something" audible to note attack.
JM2C