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Messages - rowdy_riemer

Pages: [1] 2 3 ... 16
1
Schematics and Layouts / Re: Digital JFET Test Rig
« on: December 31, 2012, 06:17:40 PM »
"and when asked about parts availability, they said they made their own transistors at the University.  "  Excellent!!

2
Schematics and Layouts / Re: Digital JFET Test Rig
« on: December 21, 2012, 11:19:43 PM »
Hehehe, we'll see if I actually get to follow up on that idea. I like your name for that concept, btw!

3
Schematics and Layouts / Re: Digital JFET Test Rig
« on: December 20, 2012, 09:13:24 AM »
BTW, Thanks, JM!

4
Software / Re: Tgen - Free software - Audio Functions generator (Windows)
« on: December 19, 2012, 09:28:55 PM »
COOL!

5
Schematics and Layouts / Re: Digital JFET Test Rig
« on: December 19, 2012, 09:09:05 PM »
BTW, has anyone considered making their own JFET's? I've been thinking about the possibility of making a JFET with an aluminum-doped zinc-oxide channel and a copper II oxide gate. My choice of materials are simply based on the fact that making zinc oxide and copper II oxide at home is probably easier than making your own silicon JFET's. I did see a video somewhere where some very intelligent woman made her own MOSFET at home, though she did have some equipment that one wouldn't normally find at home.

I'd first probably see if I could produce a small rod of zinc chloride. I saw some documentation where powdered zinc oxide was packed into a... I think a rod... and then sintered at 600 degrees C. I read somewhere else where a bit of aluminum chloride can be used to boost conductivity. If I could succeed at producing a conductive zinc-oxide rod, then, I would work out how to bond aluminum oxide to it for a gate. If I could ever get to that point, maybe I would play with channel and gate geometries, doping, etc. to see what I could get.

6
Schematics and Layouts / Re: Digital JFET Test Rig
« on: December 19, 2012, 09:00:09 PM »
Hehehe, nope. I'm just a tinkerer. I do have an AAS in Computer Integrated Manufacturing, which no doubt shaped some of my thinking here, but I've been simply writing software, mostly in C++, for most of the career. I figured this sort of thing could be useful. I wish I had the time to see this project all the way through, even if it's just for fun.

7
Schematics and Layouts / Re: Digital JFET Test Rig
« on: December 14, 2012, 11:38:40 PM »
Someone requested the source code I used for this project, and I figured this would be a good place to post it, so here it is:

#define TEST_RIG_ENABLE_PIN 4
#define TEST_MODE_PIN 3
#define MEASUREMENT_PIN 0

#define CONVERSION_FACTOR 0.97

void setup()
{
  pinMode(TEST_RIG_ENABLE_PIN, OUTPUT);
  pinMode(TEST_MODE_PIN, OUTPUT);
  digitalWrite(TEST_RIG_ENABLE_PIN, HIGH);
  Serial.begin(9600);
  Serial.write("Initialized\n");
}
void loop()
{
  if(Serial.available() > 0)
  {
    int input = Serial.read();
   
    //if(input == 't')
    //{
      performTest();
    //}
  }
}
void performTest()
{
  digitalWrite(TEST_RIG_ENABLE_PIN, LOW);
  Serial.write("Performing Test\n");
 
  float Vpp = getVpp();
  Serial.write("Vpp = ");
  Serial.print(Vpp);
  Serial.write(" V\n");

  float Idss = getIdss();
  Serial.write("Idss = ");
  Serial.print(Idss * 1000);
  Serial.write(" mA\n");
 
  digitalWrite(TEST_RIG_ENABLE_PIN, HIGH);
  Serial.write("Test Complete\n");
}
float getVpp()
{
  digitalWrite(TEST_MODE_PIN, HIGH);
 
  float value = 0;
  float accumulatedValue = 0;
  int numberOfSamples = 10000;
 
  for(int iteration = 0; iteration < numberOfSamples; ++iteration)
    accumulatedValue += analogRead(MEASUREMENT_PIN);

  value = accumulatedValue/numberOfSamples;
  value = value/-1024 * 5 * CONVERSION_FACTOR;
 
  return(value);
}
float getIdss()
{
    digitalWrite(TEST_MODE_PIN, LOW);
 
    float value = 0;
    float accumulatedValue = 0;
    int numberOfSamples = 10000;
   
    for(int iteration = 0; iteration < numberOfSamples; ++iteration)
      accumulatedValue += analogRead(MEASUREMENT_PIN);
 
    value = accumulatedValue/numberOfSamples;
    value = value/1024 * .05 * CONVERSION_FACTOR;
   
    return(value);
}

8
Amplifier Discussion / Re: Speaker Attenuator Idea with Reactive Load
« on: April 22, 2012, 02:06:13 AM »
Ok, I've had a little time to look at this again, and I realize I made a pretty retarded mistake with my last revision. I accidentally hooked the output of both sampling resistors to the same input on the op amp, putting them in parallel. No wonder the voltages across them matched so well.  :duh

9
Amplifier Discussion / Re: Speaker Attenuator Idea with Reactive Load
« on: April 15, 2012, 12:27:48 PM »
I'll try to find it. Did it use a reactive load that mimicked the actual speaker's reactance? I'm sure there's reamping attenuators that do, but I haven't come across a description of one yet. I should look in Teemu's book.

10
Amplifier Discussion / Re: Speaker Attenuator Idea with Reactive Load
« on: April 15, 2012, 01:22:53 AM »
BTW, if it looks like I should have seen many of these problems from the beginning, understand that I don't have a lot of time to spend on this. I've got WAY more physics homework than I can possibly finish, and I've got an Essay for another class due soon. I'm working on this here and there when I get a chance.

11
Amplifier Discussion / Re: Speaker Attenuator Idea with Reactive Load
« on: April 15, 2012, 01:21:18 AM »
The above changes significantly improve the performance of this idea. The current through the simulated load closely follows the current through the simulated speaker load. There is still a problem, though. If I attenuate the signal to the output amplifier, things fall apart. I'll figure it out though. :) I guess I'd better. If it doesn't attenuate the output, the whole thing is a bit pointless.

12
Amplifier Discussion / Re: Speaker Attenuator Idea with Reactive Load
« on: April 15, 2012, 01:16:45 AM »
Ok, some significant improvements. The inputs of the op-amp comparing the voltages across the sampling resistors now have a midpoint bias upon which the ac voltages of the sampling resistors are imposed. This prevents the dc current of the active load from messing up the comparison.


13
Amplifier Discussion / Re: Speaker Attenuator Idea with Reactive Load
« on: April 14, 2012, 07:51:24 PM »
Here's a more developed version of the idea. R7 and R8 simulate the speaker load. R4 and R5 are supposed to be dual-ganged pots. In multisim, this basically works, though there are issues to work out. The Reactive load increases and decreases as I change the R7/R8 simulated speaker load. But the current is close to double what is going through the simulated speaker load at 8 ohms and about half that at 100 ohms. Still, it works well enough for me to think this is doable. BTW, don't read too much in my source follower output stage. I'm just testing out a basic concept. I know not to run DC through a speaker. Just keeping it simple at the moment.

14
Amplifier Discussion / Re: Speaker Attenuator Idea with Reactive Load
« on: April 13, 2012, 09:06:33 PM »
A little rearranging of things fixes the problem. I'll post more after doing some simulation.

15
Amplifier Discussion / Re: Speaker Attenuator Idea with Reactive Load
« on: April 13, 2012, 08:01:25 PM »
Damn, just saw a glaring error. From an AC perspective, Q1 is parallel to Rs1, not R1.

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