Quote from: LOBO on April 14, 2011, 11:45:25 AM
I hope Mensur don't mind: http://www.megaupload.com/?d=VFD4E6KP

I don't mind:
http://img641.imageshack.us/img641/4237/ultimaterandall.jpg

You can devalue R22 to 1.5K, C12 to 1uF, and go the same with R23 C21, but there's possibility of oscillation.Why would you need more gain on the clean?

Quote from: Alexius II on March 21, 2011, 04:55:00 PM
So the only thing I have to change is to re-set the drain voltage of first two stages? That is great to hear! 

I'm away from home until friday, so I won't be able to try it out until then. I will report back on how it sounds  :tu:

By the way, how would one change (lower) the gain of the mu stage, if lower gain would be required? I found the "original" mu-amp here, but this does not help my understanding of this stage. I can see that ROG added 390R source resistors, somewhat changed the "bias" resistors (two 10k and a 1M instead of two 10M) and the input resistor is changed from 10M to 220k. Does someone have a simple explanation of this configuration?

Actually it's a pretty simple stage, you see 390R is stage biasing resistor, the upper fet is current source, meaning(active load), varying potential divider i.e. 10K's you will send less dc voltage on the gate of the upper one, hence, smaller current you will get on the source,
100nF cap is there to determine low freq response of the stage. Here, low freq response is 1.59Hz - 3dB's, which is pretty low, but you can try 22nF, or 2.2nF,just to keep bass tight.
Here's an example, If we have a JFET that has VGS 7V, and maximum current of 12mA, then, we will have 4.5VDC on the gate of the upper FET(9VDC-10K-10K potencial divider gives 4.5VDC), so current on the source will be around 9mA, continuous, so that is our maximum current on the stage, or you can set 1K resistor directly form a supply(9VDC/1K=9mA).

Cheers

Quote from: phatt on January 30, 2011, 07:31:29 AM
Hi Steve,
             Your Valve section may need some fine tuning.
i.e. add some series resistance after each triode,, you've got some ugly blocking type distortion which is destroying the sound. (but if that spitting distortion is to your taste then go for it.)

You may wish to look at the redneF Pro Junior preamp setup for some good ideas.
Or even some early Deluxe tone circuits might interest you.

Other than that It's a *Very clever idea* and good on you for having a go.
Thanks for sharing your ideas. :tu:

If it interests you I have had good results by power soaking a small PP Amp and ReAmplifiying it via a simple voltage divider setup and then into a large 120Watt SS Amp. (You get to do post power tube EQ effects that way)
Cheers, Phil.

Phil can you post the schematic of that, it;s very interesting?

What's the problem with PSU?

Here's what's new:
http://img826.imageshack.us/img826/4341/randallultimate.png

We have standard Randall RG100ES with contour control(which is from Century 200), which can be bypassed, plus it has additional gain stage for accommodating volume drop due to diode clipping.

Quote from: LOBO on November 09, 2010, 02:21:31 PM
Mensur, i would like to ask you again about the capacitors  c5, c8 & c14. Are they normal (film, poly etc ) or eletrolitical (polarized) ? Cuz their values are 1uF...

tankx for the previous answers.

I personaly like film caps(Wima MKS4) overthere, but you can try with elcos, and see what best suites you.

Thanks,
The clipping diodes are in the circuit, before master contol.
It has +1 gain stage to acomodate signal loss after clipping diodes.
All Randall's have the same tonestack, Warhead has parametric mid control, which uses OpAmps, and I dont like opamps, so I did it like this.

I used 24V PSU with 2N5484 FET's which are almost like 12AX7,or enhanced version of it
(low input capacitance like 12AX7, low output resistance, same current at lower voltages).
My layout is well designed, so it has no oscillations, star grounded, voltage ground is way out of the way of signal ground.The size of the PCB is only problem, but I'm not worried for that.
What else do you want to know?

No problem bro(nema problema burazeru :tu:),
Here's layout, and the final schematic:

I must qoute myself, somebody doesn't read all the posts

Quote from: mensur on September 25, 2010, 06:08:07 PM
Use MPF102's for both, voltage gain and as buffer.
Use 680R for RS(voltage gain) without bypass cap, BTW. Cs reduce internal resistance of the channel, hence more gain.As for Rd use 2.2K.
These are resistance values foe MPF102 FET (with -4.5V, 13.5mA Idss characteristics).
From my cacs. it will bring you to -2.12V of Vg(humbacker sweetspot) and 3.46mA Id.
Gain will be around 3 to 4x.As for buffer use same character. FET with 2.7K Rs, everything else remains the same.I don't like bipolars as buffers, you don't need much current there.

You are right :tu:

Quote from: Alexius II on September 26, 2010, 04:11:09 PM
I was a kid and bit too young to remember anything from the old Yugoslavia, but they say that were the good times  

Anyway, thank you both. I went through some online theory pages and found a few other equations that helped me understand the few missing relations. I think I get it now... I hope :duh


I will now go again through the calculations for my transistor:

These are the equations I used for the gain stage:

Vgs = -Id*Rs
Vds = Vdd-Id*(Rd+Rs)
Id = Idss*(1-(Vgs/Vp))^2 (the characteristic curve is drawn from this equation)
gm0 = 2*IDSS/VP
gm = gm0*(1-(VGS/VP))
Av = (gm*Rd)/(1+gm*Rs) (if there is no Cs)

My transistor:
MPF102
Vp = -4.5V
Idss = 13.5mA

I choose Vgs to be 1/2 of Vp, so
Vgs: 0.5*(-4.5V) = -2.25V

Id = 13.5mA*(1-(2.25V/4.5V))^2 = 13.5mA * 1/4 = 3.375mA
Rs = Vgs/Id = 2.25V/3.375mA = 666ohm (closest is 680R)

gm0 = 2*13.5mA/4.5V = 0.006mS
gm = 0.006mS*(1-(2.25V/4.5V)) = 0.003mS

Then I choose Rd. I understand that with larger Rd come larger voltage gain and output impedance + lower current.

Rd = 2.2k  (18V/2200R = 0.0081A = 8mA)
Av = (0.003mS*2200R)/(1+0.003mS*680R) = 2.17 (= 6.7dB)


Ok, I hope everything is OK this far.

Then comes the buffer (aka "source follower" or "common drain amplifier")  
Only the Rs is necessary to bias it. I've read some theory about it, but I'm not sure. The way I understood it, you have to choose Rs in a way, that at the source you have half the voltage (Vcc). If this is correct, I then used the identical MPF102 transistor with calculated Id = 3.375mA (for Vgs = 1/2 Vp) inserted in the equation:

1/2 Vcc = 9V = 3.357mA * Rs
Rs = 9V / 0.003357A = 2680R = 2.7k

Is this ok, or am I making things up?  :loco  

Use MPF102's for both, voltage gain and as buffer.
Use 680R for RS(voltage gain) without bypass cap, BTW. Cs reduce internal resistance of the channel, hence more gain.As for Rd use 2.2K.
These are resistance values foe MPF102 FET (with -4.5V, 13.5mA Idss characteristics).
From my cacs. it will bring you to -2.12V of Vg(humbacker sweetspot) and 3.46mA Id.
Gain will be around 3 to 4x.As for buffer use same character. FET with 2.7K Rs, everything else remains the same.I don't like bipolars as buffers, you don't need much current there.

No problem bro,
Yea, the calcs are only for gain stage only.
The value of Rs on the buffer the determine voltage gain of the buffer, as so the output impedance of the buffer, but that is negligible.It also determines quiescent current of the FET,just as s regular Rs.
In our case the Vgs is higher than the Vgs(off), which is about 10V.
The gain of the buffer is:Av= (gm x Rs) / (1 + (gm X Rs))
Output impedance is:Zo= (Rs x (1/gm)) / (Rs + (1/gm))
Put 10K and you will be fine.

The buffer will not clip cause you've done the same thing with DC coupling as with voltage divider.
The best thing for you is to take 2N5486 FET's, for voltage gain, as so as buffer.
Fet are just like the triodes(but only enhanced one's)
I will give you the example:
Lets say that our 2N5486 have Vgs off -3V, and 12mA of current(you can find that info on the datasheet, transfer characteristics),
We want that maximum current consumption be 10mA(we get that from Ohm's law: 18V/10mA=1800R or 1.8K, that is our Rd)
We want linear operation,so we chose mid point of VGS(off): -3 / 2 = -1.5V,and Id form the trans.characteristics is about 3.5mA, so Rs will be -1.5V / 3.5mA= 428R or, 430R.
We get voltage gain from this formula:
Av = gm x Rd (bypassed Rs, for Cs use 10uF el.cap, corner freq will be 37Hz),
gm will be gm= gm0 x ( 1 - (VGS / VP ))
gm0 will be: gm0= 2xIDSS / VP
So,
Idss=12mA
Vp(or Vgsoff)=-3V
gm0= 2xIDSS / VP=2*12mA/-3V=0.008mS
gm= gm0 x ( 1 - (VGS / VP ))=0.004mS
Av=0.004mS * 1.8K = 7.2x or 17.15dB's

Omit 1M + 1M voltage divider, cause you've already have DC voltage on the gate of a buffer.
1.You don't mess up the frequencies, simpler the deign, greater the tone.
2.Yes, I meant those DC blocking capacitors, pot and the divider.Cause we want to make it simpler.
3.After the 1uF(use wima MKS4 63V poly cap),put 10K log pot.If you use active pickups, you don't need buffer, hence you already have low output resistance,and decent voltage gain.
4.Measure the current of each FET, you will do that, if you tie gate and source together, and conect - of 9V battery to them, and drain of the FET tie to the mA meter and +9V.

Quote(I study something completely different, so this is just my free-time "hobby")

Tell me about that, I finished Faculty of sport and physical education, on the department of sport management, and higher degree of tennis trainee