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Question about SRPP "mu" FET gain stage

Started by armstrom, February 09, 2009, 09:53:34 PM

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armstrom

I've been playing around with some spice simulations of a basic mu amp. In my case I simulated the first gain stage of the blackface preamp found here: http://www.redcircuits.com/Page120.htm

My question relates to controlling the gain of these stages. In my simulation it seems C1 from the linked schematic (the cap from the gate to the source on the upper FET) has a huge effect on the gain of the circuit. Is this, in fact, the easiest way to control the gain? My simulations didn't show any serious change in distortion characteristics by just changing the cap because it doesn't affect the bias point of the stage.

Is it really that simple? I know simulations aren't perfect so I'm wondering if there's some real-world interaction that I'm missing.

I've attached a LTSpice file of the circuit in case anyone wants to play around with it.

J M Fahey

Dear Armstrom. There´s something weird here. C1 is meant to NOT affect gain, at least within the audio band; it will be "flat" from a certain "cutoff frequency" upwards.
The cutoff frequency for an RC network 47k/47uF is around 0.068 Hz. The 47K comes from considering both 100K biasing resistors in parallel for audio purposes.
C1´s value would affect gain if you punched in , say, a 48 PICO farad instead of 47 MICRO farad.
Please check your simulation.
Bye.

armstrom

Hmm.. you're right. I re-ran my simulation here at work (with the same file) and got the behavior you describe. I'll have to check when I get home but I'm quite sure that varying C1 changed the gain when I tested it there. Here at work the gain only responds to changes in the voltage divider network biasing the top JFET.
-Matt